ST7LITE49M datasheet(55/188 Pages) STMICROELECTRONICS

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ST7LITE49M

Interrupts

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8.5

Description of interrupt registers

8.5.1

CPU CC register interrupt bits

Reset value: 111x 1010(xAh)

Bit 5, 3 = I1, I0 Software Interrupt Priority bits

These two bits indicate the current interrupt software priority (see Table 14).

These two bits are set/cleared by hardware when entering in interrupt. The loaded

value is given by the corresponding bits in the interrupt software priority registers

(ISPRx).

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and

PUSH/POP instructions (see Table 16: Dedicated interrupt instruction set).

TRAP and RESET events can interrupt a level 3 program.

8.5.2

Interrupt software priority registers (ISPRx)

All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only.

Reset value: 1111 1111 (FFh)

ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt

vector (except RESET and TRAP) has corresponding bits in these registers to define its

software priority. This correspondence is shown in Table 15.

Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0

bits in the CC register.

Read/write

Table 14.

Setting the interrupt software priority

Interrupt software priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable*)

ISPR0

I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

I1_0

I0_0

ISPR1

I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

ISPR2

I1_11

I0_11

I1_10

I0_10

I1_9

I0_9

I1_8

I0_8

ISPR3

111

I1_12

I0_12

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