ST7LITE49M datasheet(47/188 Pages) STMICROELECTRONICS

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ST7LITE49M

Supply, reset and clock management

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7.5.4

CLOCK Controller Control/Status register (CKCNTCSR)

Reset value: 0000 1001 (09h)

Bits 7:4 = Reserved, must be kept cleared.

Bit 3 = AWU_FLAG AWU Selection bit

This bit is set and cleared by hardware.

0: No switch from AWU to RC requested

1: AWU clock activated and temporization completed

Bit 2 = RC_FLAG RC Selection bit

This bit is set and cleared by hardware.

0: No switch from RC to AWU requested

1: RC clock activated and temporization completed

Bit 1 = Reserved, must be kept cleared.

Bit 0 = RC/AWU RC/AWU Selection bit

0: RC enabled

1: AWU enabled (default value)

7.5.5

System Integrity (SI) Control/Status register (SICSR)

Reset value: 011x 0x00 (xxh)

Bit 7 = Reserved, must be kept cleared

Bits 6:5 = CR[1:0] RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately

after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer

to Section 7.1.1: Internal RC oscillator on page 34.

Bit 4 = WDGRF Watchdog Reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is

set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD

Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

The WDGRF and the LVDRF flags are used to select the reset source (see Table 11).

AWU_FLAG

RC_FLAG

RC/AWU

Read/write

CR1

CR0

WDGRF

LVDRF

AVDF

AVDIE

Read/write

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