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STR710FZ2T6 データシート(PDF) 45 Page - STMicroelectronics |
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STR710FZ2T6 データシート(HTML) 45 Page - STMicroelectronics |
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45 / 77 page  STR71xF Electrical parameters 45/77 Table 21. PLL2 characteristics Symbol Parameter Test Conditions Value Unit Min Typ Max fPLLCLK2 PLL multiplier output clock fPLL x 28 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Table 22. Low-power mode wake-up timing Symbol Parameter Typ Unit tWULPWFI Wake-up from LPWFI mode 26(1) 1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down µs tWUSTOP Wake-up from STOP mode 2048 CLK Cycles tWUSTBY Wake-up from STANDBY mode 2048 CLK Cycles + 8 CLK2 Cycles(2) 2. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084) Cycles |
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