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ST10F271B データシート(PDF) 103 Page - STMicroelectronics

部品番号 ST10F271B
部品情報  16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
PDF  180 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F271B データシート(HTML) 103 Page - STMicroelectronics

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ST10F271B/ST10F271E
System reset
103/180
20.9
Reset summary
A summary of the different reset events is reported in the table below.
Table 49.
Reset event
Event
RSTIN
WDTCON Flags
min
max
Power-on Reset
0
0
N
Asynch.
1 ms (VREG)
1.2 ms
(Reson. + PLL)
10.2 ms
(Crystal + PLL)
-
1
1110
0
1
N
Asynch.
1ms (VREG)
-
1
1110
1
x
x
FORBIDDEN
x
x
Y
NOT APPLICABLE
Hardware Reset
(Asynchronous)
0
0
N
Asynch.
500ns
-
0
1110
0
1
N
Asynch.
500ns
-
0
1110
0
0
Y
Asynch.
500ns
-
0
1110
0
1
Y
Asynch.
500ns
-
0
1110
Short Hardware
Reset
(Synchronous) (1)
1
0
N
Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0
0110
1
1
N
Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0
0110
10
Y
Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0
0110
Activated by internal logic for 1024 TCL
11
Y
Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0
0110
Activated by internal logic for 1024 TCL
Long Hardware
Reset
(Synchronous)
10
N
Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0
1110
11
N
Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0
1110
10
Y
Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0
1110
Activated by internal logic only for 1024 TCL
11
Y
Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0
1110
Activated by internal logic only for 1024 TCL



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