ST10F271B datasheet(24/180 Pages) STMICROELECTRONICS

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Memory organization

ST10F271B/ST10F271E

24/180

ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The

ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON

(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64MHz

CPU clock. No tristate waitstate is used.

SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The

SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON

(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz

CPU clock. No tristate waitstate is used.

I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is

enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.

Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word

accesses are possible). Two waitstates give an access time of 62.5ns at 64MHz CPU clock.

No tristate waitstate is used.

X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set

of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON

demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two

waitstates give an access time of 62.5ns at 64MHz CPU clock. No tristate waitstate is used.

The following set of features are provided:

●

CLKOUT programmable divider

●

XBUS interrupt management registers

●

ADC multiplexing on P1L register (only for ST10F271E)

●

Port1L digital disable register for extra ADC channels

●

CAN2 multiplexing on P4.5/P4.6

●

CAN1-2 main clock prescaler

●

Main Voltage Regulator disable for power-down mode

●

TTL / CMOS threshold selection for Port0, Port1, and Port5.

In order to meet the needs of designs where more memory is required than is provided on

chip, up to 16M Bytes of external memory can be connected to the microcontroller.

Visibility of XBUS peripherals

In order to keep the ST10F271 compatible with the ST10F168 / ST10F269, the XBUS

peripherals can be selected to be visible on the external address / data bus. Different bits for

X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the

global enabling with XPEN bit in SYSCON register, the corresponding address space, port

pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and

not available. Refer to

Chapter 23: Register set on page 112.

ST10F271B データシート(PDF) 24 Page - STMicroelectronics

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