ST10F271B datasheet(19/180 Pages) STMICROELECTRONICS

19 / 180 page

ST10F271B/ST10F271E

Pin data

19/180

P1L.0 - P1L.7

P1H.0 -

P1H.7

118-125

128-135

I/O

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the corresponding

output driver to high impedance state. PORT1 is used as the 16-bit address bus

(A) in demultiplexed bus modes: if at least BUSCONx is configured such the

demultiplexed mode is selected, the pis of PORT1 are not available for general

purpose I/O function. The input threshold of Port 1 is selectable (TTL or CMOS).

Only for the ST10F271E

– The pins of P1L also serve as the additional (up to 8) analog input channels for

the A/D converter, where P1L.x equals ANy (Analog input channel y,

where y = x + 16). This additional function have higher priority on demultiplexed

bus function.

The following PORT1 pins have alternate functions:

132

P1H.4

CC24IO

CAPCOM2: CC24 capture input

133

P1H.5

CC25IO

CAPCOM2: CC25 capture input

134

P1H.6

CC26IO

CAPCOM2: CC26 capture input

135

P1H.7

CC27IO

CAPCOM2: CC27 capture input

XTAL1

138

XTAL1

Main oscillator amplifier circuit and/or external clock input.

XTAL2

137

XTAL2

Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2

unconnected. Minimum and maximum high / low and rise / fall times specified in

the AC Characteristics must be observed.

XTAL3

143

XTAL3

32 kHz oscillator amplifier circuit input

XTAL4

144

XTAL4

32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,

XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32

in RTCCON register shall be set. 32 kHz oscillator can only be driven by an

external crystal, and not by a different clock source.

RSTIN

140

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for

a specified duration while the oscillator is running resets the ST10F271. An

internal pull-up resistor permits power-on reset using only a capacitor connected

to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON

sequence.

RSTOUT

141

Internal Reset Indication Output. This pin is driven to a low level during hardware,

software or watchdog timer reset. RSTOUT remains low until the EINIT (end of

initialization) instruction is executed.

NMI

142

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU

to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when

the PWRDN (power down) instruction is executed, the NMI pin must be low in

order to force the ST10F271 to go into power down mode. If NMI is high and

PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal

mode.

If not used, pin NMI should be pulled high externally.

VAREF

A/D converter reference voltage and analog supply

VAGND

A/D converter reference and analog ground

Table 1.

Pin description (continued)

Symbol

Type

Function

ST10F271B データシート(PDF) 19 Page - STMicroelectronics

ST10F271B データシート(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード