ST10F271B datasheet(31/180 Pages) STMICROELECTRONICS

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ST10F271B/ST10F271E

Internal Flash memory

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5.4.2

Flash control register 0 high

The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low

(FCR0L) is used to enable and to monitor all the write operations on the IFLASH. The user

has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by

the user in Bootstrap Mode only.

FCR0H (0x08 0002)

FCR

Reset value:

0000h

765

210

WMS

SUSP

WPG DWPG

SER

reserved

SPR

reserved

Table 8.

Flash control register 0 high

Bit

Function

SPR

Set Protection

This bit must be set to select the Set Protection operation. The Set Protection

operation allows to program 0s in place of 1s in the Flash Non Volatile Protection

Registers. The Flash Address in which to program must be written in the FARH/L

registers, while the Flash Data to be programmed must be written in the FDR0H/L

before starting the execution by setting bit WMS. A sequence error is flagged by bit

SEQER of FER if the address written in FARH/L is not in the range 0x0E8FB0-

0x08DFBF. SPR bit is automatically reset at the end of the Set Protection

operation.

SER

Sector Erase

This bit must be set to select the Sector Erase operation in the Flash modules. The

Sector Erase operation allows to erase all the Flash locations to value 0xFF. From

1 to all the sectors of the same Bank (excluded Test-Flash for Bank B0) can be

selected to be erased through bits BxFy of FCR1H/L registers before starting the

execution by setting bit WMS. It is not necessary to pre-program the sectors to

0x00, because this is done automatically. SER bit is automatically reset at the end

of the Sector Erase operation.

DWPG

Double Word Program

This bit must be set to select the Double Word (64 bits) Program operation in the

Flash module. The Double Word Program operation allows to program 0s in place

of 1s. The Flash Address in which to program (aligned with even words) must be

written in the FARH/L registers, while the 2 Flash Data to be programmed must be

written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word)

before starting the execution by setting bit WMS. DWPG bit is automatically reset

at the end of the Double Word Program operation.

WPG

Word Program

This bit must be set to select the Word (32 bits) Program operation in the Flash

module. The Word Program operation allows to program 0s in place of 1s. The

Flash Address to be programmed must be written in the FARH/L registers, while

the Flash Data to be programmed must be written in the FDR0H/L registers before

starting the execution by setting bit WMS. WPG bit is automatically reset at the

end of the Word Program operation.

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