AD4056BCPZ-R2 datasheet(65/67 Pages) AD

65 / 67 page

Data Sheet

AD4050/AD4056

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Rev. A | 65 of 67

Table 51. Bit Descriptions for DEVICE_STATUS

Bits

Bit Name

Description

Reset

Access

DEVICE_READY

Device Ready Bit. This bit is automatically set to 1 when the device reset and startup sequence is

complete and is ready for serial communications from the digital host.

0x0

DEVICE_RESET

Device Reset Detection Bit. Indicates a device reset occurred. This bit is cleared by setting it to 1.

0x1

R/W1C

INTERFACE_ERR

Interface Error Bit. Indicates if one or more interface communication errors occurs. This bit is the logical

OR of all bits in INTERFACE_STATUS register.

0x0

THRESH_OVERRUN

Threshold Overrun Bit. This bit is set to 1 when a threshold overrun event is detected. This bit is sticky

and is only cleared by writing it to a 1.

0x0

R/W1C

MAX_FLAG

Maximum Threshold Alert Bit. This bit is set to 1 when a maximum threshold violation is detected. This

bit is sticky and is only cleared by writing it to a 1.

0x0

R/W1C

MIN_FLAG

Minimum Threshold Alert Bit. This bit is set to 1 when a minimum threshold violation is detected. This bit

is sticky and is only cleared by writing it to a 1.

0x0

R/W1C

OVER_RNG_ERR

Overrange Error. Write 1 to clear.

0x0

R/W1C

UNDER_RNG_ERR

Underrange Error. Write 1 to clear.

0x0

R/W1C

MAXIMUM INTERRUPT SAMPLE REGISTER

Address: 0x42 − 0x43, Reset: 0x0000, Name: MAX_SAMPLE_REG

Table 52. Bit Descriptions for MAX_SAMPLE_REG

Bits

Bit Name

Description

Reset

Access

[15:0]

MAX_SAMPLE

Maximum Interrupt Sample Result. Contains ADC result generated by maximum threshold interrupt in

trigger mode. Uses the same data format (twos complement or straight binary) as the ADC as set by

the DATA_FORMAT bit.

0x0

MINIMUM INTERRUPT SAMPLE REGISTER

Address: 0x44 − 0x45, Reset: 0x0000, Name: MIN_SAMPLE_REG

Table 53. Bit Descriptions for MIN_SAMPLE_REG

Bits

Bit Name

Description

Reset

Access

[15:0]

MIN_SAMPLE

Minimum Interrupt Sample Result. Contains ADC result generated by minimum threshold interrupt in

trigger mode. Uses the same data format (twos complement or straight binary) as the ADC as set by

the DATA_FORMAT bit.

0x0

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