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68HC05PL4B データシート(PDF) 93 Page - Freescale Semiconductor, Inc

部品番号 68HC05PL4B
部品情報  Industry standard 8-bit M68HC05 CPU core
PDF  98 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

68HC05PL4B データシート(HTML) 93 Page - Freescale Semiconductor, Inc

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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
A-3
PGM – EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT
≠ 1,
then PGM = 0.
A.4.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time tPGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
CAUTION
It is important to remember that an external programming voltage
must be applied to the VPP pin while programming, but it should be
equal to VDD during normal operations.
Figure A-2
shows the o w required to successfully program the EPROM.
A.5
EPROM PROGRAMMING SPECIFICATIONS
Table A-2. EPROM Programming Electrical Characteristics
(VDD = 4V ±10%, VSS = 0 Vdc, TA = 0°C to +70°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Programming Voltage
VPP
—
12.5
—
V
Programming Current
IPP
—
5
10
mA
Programming Time per byte
tEPGM
—1—
ms
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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