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LAN9252/ML データシート(PDF) 244 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 244 Page - Microchip Technology

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LAN9252
DS00001909A-page 244
 2015 Microchip Technology Inc.
12.14.26 ASIC CONFIGURATION REGISTER
Note 12:
The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu-
rable Registers," on page 201 for additional information.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.27 RESERVED REGISTER
Note 13:
The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu-
rable Registers," on page 201 for additional information.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
0142h-0143h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15
MI Link Detection
(Link configuration, link detection, registers PHY Port Status
Registers)
0:
Not available
1:
MI Link Detection Active
RO
RO
0b
Note 12
14:6
RESERVED
RO
RO
0000000b
Note 12
7
MI Write Gigabit Register 9 Enable
Enables writes to PHY register 9 for PHYs which use this regis-
ter per IEEE 802.3
0:
MI writes to Gigabit register 9 disabled
1:
MI writes to Gigabit register 9 enabled
RO
RO
0b
Note 12
6:0
RESERVED
RO
RO
0000000b
Note 12
Offset:
0144h-0145h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:0
RESERVED
RO
RO
0000h
Note 13



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