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LAN9252/ML データシート(PDF) 245 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 245 Page - Microchip Technology |
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245 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 245 LAN9252 12.14.28 PDI CONFIGURATION REGISTER The bit definitions of this register are dependent on the selected PDI mode (Process Data Interface field in the PDI Con- trol Register): Digital I/O Mode or HBI Modes. PDI Configuration Register: Digital I/O Mode Note 14: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu- rable Registers," on page 201 for additional information. Offset: 0150h Size: 8 bits Bits Description ECAT Type PDI Type Default 7:6 Output Data Sample Selection 00: End of Frame 01: RESERVED 10: DC SYNC0 event 11: DC SYNC1 event Note: If OUTVALID Mode = 1, output DATA is updated at Process Data Watchdog trigger event (Output Data Sample Selection bit ignored) RO RO 00b Note 14 5:4 Input Data Sample Selection 00: End of Frame 01: Rising edge of LATCH_IN 10: DC SYNC0 event 11: DC SYNC1 event RO RO 00b Note 14 3 Watchdog Behavior 0: Outputs are reset immediately after watchdog expires 1: Outputs are reset with next output event that follows watchdog expiration RO RO 0b Note 14 2 Unidirectional/Bidirectional Mode 0: Unidirectional Mode: input/output direction of pins configured individually 1: Bidirectional Mode: all I/O pins are bidirectional, direction con- figuration is ignored RO RO 0b Note 14 1 OUTVALID Mode 0: Output event signaling 1: Process Data Watchdog trigger (WD_TRIG) signaling on OUTVALID. Output data is updated if watchdog is triggered. Overrides Output Data Sample Selection bit. RO RO 0b Note 14 0 OUTVALID Polarity 0: Active high 1: Active low RO RO 0b Note 14 |
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