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LAN9252/ML データシート(PDF) 278 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 278 Page - Microchip Technology

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LAN9252
DS00001909A-page 278
 2015 Microchip Technology Inc.
12.14.64 SYSTEM TIME REGISTER
Note 38:
When writing via ECAT, the control loop is triggered to process the new value.
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
12.14.65 RECEIVE TIME ECAT PROCESSING UNIT REGISTER
Note:
For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the
highest address.
Offset:
0910h-0917h
Size:
64 bits
Bits
Description
ECAT
Type
PDI
Type
Default
63:0
ECAT Read Access:
Local copy of the System Time when the frame passed the refer-
ence clock (i.e., including System Time Delay). Time latched at
beginning of the frame (Ethernet SOF delimiter).
PDI Read Access:
Local copy of the System Time. Time latched when reading first
byte (0910h).
RO
RO
00000000h
00000000h
31:0
Write Access:
Written value will be compared with the local copy of the system
time. The result is an input to the time control loop.
Note:
Written value will be compared at the end of the frame
with the latched (SOF) local copy of the system time
if at least the first byte (0910h) was written.
W
Note 38
RO
00000000h
Offset:
0918h-091Fh
Size:
64 bits
Bits
Description
ECAT
Type
PDI
Type
Default
63:0
Local time of the beginning of a frame (start first bit of preamble)
received at the ECAT Processing Unit containing a write access
to Receive Time Port 0 Register (0900h).
Note:
If port 0 is open, this register reflects the Receive
Time Port 0 Register as a 64-bit value.
RO
RO
00000000h
00000000h



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