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LAN9252/ML データシート(PDF) 279 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 279 Page - Microchip Technology |
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279 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 279 LAN9252 12.14.66 SYSTEM TIME OFFSET REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.67 SYSTEM TIME DELAY REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.68 SYSTEM TIME DIFFERENCE REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0920h-0927h Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 Difference between local time and System Time. Offset is added to local time. Local time of the beginning of a frame (start first bit of preamble) received at the ECAT Processing Unit containing a write access to Receive Time Port 0 Register (0900h). Note: If port 0 is open, this register reflects the Receive Time Port 0 Register as a 64-bit value. R/W RO 00000000h 00000000h Offset: 0928h-092Bh Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 Delay between Reference Clock and the ESC. R/W RO 00000000h Offset: 092Ch-092Fh Size: 32 bits Bits Description ECAT Type PDI Type Default 31 0: Local copy of System Time greater than or equal to received System Time 1: Local copy of System Time smaller than received System Time RO RO 0b 30:0 Mean difference between local copy of System Time and received System Time values. RO RO 00000000h |
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