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データシートサーチシステム |
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データシートサーチシステム |
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ADC12L034 データシート(PDF) 7 Page - National Semiconductor (TI) |
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ADC12L034 データシート(HTML) 7 Page - National Semiconductor (TI) |
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7 / 35 page  AC Electrical Characteristics (Continued) The following specifications apply for V + =V A+=VD+ = +3.3 VDC,VREF+ = +2.500 VDC,VREF−=0VDC, 12-bit + sign conver- sion mode, t r =tf = 3 ns, fCK =fSK = 5 MHz, RS =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.250V common-mode voltage, and 10(t CK) acquisition time unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. (Note 17) Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units (Limits) t A Acquisition Time (Note 19) 6 Cycles Programmed 6(t CK) 6(t CK) (min) 7(t CK) (max) 1.2 µs (min) 1.4 µs (max) 10 Cycles Programmed 10(t CK) 10(t CK) (min) 11(t CK) (max) 2.0 µs (min) 2.2 µs (max) 18 Cycles Programmed 18(t CK) 18(t CK) (min) 19(t CK) (max) 3.6 µs (min) 3.8 µs (max) 34 Cycles Programmed 34(t CK) 34(t CK) (min) 35(t CK) (max) 6.8 µs (min) 7.0 µs (max) t CAL Self-Calibration Time 4944(t CK) 4944(t CK) (max) 988.8 µs (max) t AZ Auto-Zero Time 76(t CK) 76(t CK) (max) 15.2 µs (max) t SYNC Self-Calibration or Auto-Zero Synchronization Time from DOR 2(t CK) 2(t CK) (min) 3(t CK) (max) 0.40 µs (min) 0.60 µs (max) t DOR DOR High Time when CS is Low Continuously for Read Data and Software Power Up/Down 9(t SK) 9(t SK) (max) 1.8 µs (max) t CONV CONV Valid Data Time 8(t SK) 8(t SK) (max) 1.6 µs (max) t HPU Hardware Power-Up Time, Time from PD Falling Edge to EOC Rising Edge 250 700 µs (max) t SPU Software Power-Up Time, Time from Serial Data Clock Falling Edge to EOC Rising Edge 500 700 µs (max) t ACC Access Time Delay from CS Falling Edge to DO Data Valid 25 60 ns (max) t SET-UP Set-Up Time of CS Falling Edge to Serial Data Clock Rising Edge 50 ns (min) t DELAY Delay from SCLK Falling Edge to CS Falling Edge 0 5 ns (min) t 1H,t0H Delay from CS Rising Edge to DO TRI-STATE® R L = 3k, CL = 100 pF 70 100 ns (max) t HDI DI Hold Time from Serial Data Clock Rising Edge 5 15 ns (min) t SDI DI Set-Up Time from Serial Data Clock Rising Edge 5 10 ns (min) www.national.com 7 |
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