The following specifications apply for V

sion mode, t

Ω, source impedance for V

≤ 25Ω, fully-differential input

with fixed 1.250V common-mode voltage, and 10(t

T

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits (Note 11)

Units (Limits)

t

HDO

DO Hold Time from Serial Data Clock

Falling Edge

R

35

65

5

ns (max)

ns (min)

t

DDO

Delay from Serial Data Clock Falling

Edge to DO Data Valid

50

90

ns (max)

t

RDO

DO Rise Time, TRI-STATE to High DO

Rise Time, Low to High

R

10

40

ns (max)

t

FDO

DO Fall Time, TRI-STATE to Low DO

Fall Time, High to Low

R

15

15

40

40

ns (max)

ns (max)

t

CD

Delay from CS Falling Edge to DOR

Falling Edge

50

80

ns (max)

t

SD

Delay from Serial Data Clock Falling

Edge to DOR Rising Edge

45

80

ns (max)

C

IN

Capacitance of Logic Inputs

10

pF

C

OUT

Capacitance of Logic Outputs

20

pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude

01183006

+

pin.

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).

Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions

between 1 to 0 and 0 to +1 (see Figure 4).

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.

Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.

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