STA529Q datasheet(46/57 Pages) STMICROELECTRONICS

部品番号	STA529Q

部品情報	FFX™ audio codec with analog and digital inputs and 2 x 1.2 W (or 2 x 100 mW HP) class-D amplifier

PDF	57 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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Registers

STA529

46/57

Doc ID 13095 Rev 3

PLLCFG1

PLL configuration (MSBs)

Address:

0x15

Type:

R/W

Buffer:

Reset:

0x00

Description:

PLLCFG2

PLL configuration (LSBs)

Address:

0x16

Type:

R/W

Buffer:

Reset:

0x00

Description:

6 FRAC_CTRL:

0: default

1: PLL fractional-frequency synthesis is enabled

5:4 DITHER_DISABLE[1:0]:

00: default

1x: disables rectangular phase frequency divider dither input to fractional control

x1: disables triangular Phase Frequency Divider dither input to Fractional Control

The mentioned blocks are shown in Figure 5.

3:0 IDF[3:0]: PLL input division factor:

0000: IDF = 1 (default)

0001: IDF = 1

0010: IDF = 2

…

1111: IDF = 15

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRAC_INPUT[15:8]

7:0 FRAC_INPUT[15:8]: MSBs of FRAC_INPUT[15:0] used to set the fractional part of PLL

multiplication factor

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FRAC_INPUT[7:0]

7:0 FRAC_INPUT[7:0]: LSBs of FRAC_INPUT[15:0] used to set the fractional part of PLL

multiplication factor

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