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STAMP0 データシート(PDF) 29 Page - STMicroelectronics |
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STAMP0 データシート(HTML) 29 Page - STMicroelectronics |
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29 / 62 page ![]() STAMP0 Architecture DocID028639 Rev 1 29/62 Figure 22: PLL block internal architecture The VCO inside the PLL produces a frequency output (FVCO) proportional to the Input Control Voltage. The loop frequency divider (NDIV+FRAC) is present within the PLL loop for dividing FVCO by a factor called the Loop Division Factor (NDIV). The output of this block is FBCLK. The loop divider can be configured in fractional mode so that the overall PLL multiplication factor could be a rational number. The STAMP0 PLL provides a LOCKP signal so that the output of the Lock circuit is asserted high when the PLL enters the state of COARSE LOCK and low when the PLL is in the UNLOCK state. If the output frequency is within ±10% (approx.) of the desired frequency, the PLL is said to be in COARSE LOCK, otherwise the PLL is in the UNLOCK state. The LOCKP signal is refreshed after every 32 cycles of INFIN. This is generated based on the result of the comparison of the number of FBCLK cycles in a window of 14 INFIN cycles. The different cases generated after comparison are: If LOCKP is already at "0", then in the next refresh cycle LOCKP goes to "1" if the number of FBCLK cycles in the 14 cycle INFIN window is 13, 14 or 15. Otherwise LOCKP stays at "0" If LOCKP is already at "1", then in the next refresh cycle LOCKP goes to "0" if the number of FBCLK cycles in 14 cycle INFIN window is less than 11 or higher than 17, otherwise LOCKP stays at "1". If LOCKP is already at "1" and CLKIN disappears, LOCKP will stay at "1" though the PLL will get unlocked. The output PLL frequency can be expressed as: Equation 3 ������������������������������������������������=������������������������������������������������������������������������×�������������������������������������������������+������������������������������������������������216+2−17� where: when DITHER_DISABLE[1] =’1’, the factor 2 -17 will not be present in the formula when FRAC_CTRL=’0’ also the FRAC term will not be present in the formula. The PLL receives as input the SCK external clock and it generates a PLL_CLK frequency equal to 2048xFs. Moreover the PLL is programmed using the IDF and NDIV parameters coming from the PLL AutoConf block. Table 8: "PLL frequency values" indicates the PLL_CLK frequencies generated as a function of the SCK and FSY frequencies. Obsolete Product(s) - Obsolete Product(s) |
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