L9026 datasheet(11/60 Pages) STMICROELECTRONICS

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Input/Output

5.1

Parallel inputs (IN0, IN1)

The L9026 has two input pins, IN0 e IN1. By default In0 is connected to channel 2, In1 is connected to channel 3.

It is possible through programming MAP_IN0 and MAP_IN1 (input mapping registers) to link different channels to

each input In0 or In1 with priority assigned to MAP_IN0.

The channels are driven by the signals that are the OR combination between PWM_SPI_register status, PWM

generators (PWM generator output mapping status), IN0 and IN1. The STA_0 (status register) shows the logic

level of the input pins.

See Section 11: SPI for further details.

The status monitor works also when the device is in limp home mode. If one of the input pins (IN0 or IN1) is

asserted to "High" and the IDLE pin is set to "Low", L9026 enters in limp home mode.

5.2

Idle pin (IDLE)

The device enters in sleep state through IDLE pin when it is setted to "low" together with IN0 and IN1. Instead if

IDLE pin is in "low" state and one of the two inputs are in "high" state the device is brought in Limp home mode. In

order to ensure a correct transition IDLE pin should be set at least for a time duration of tIDLEFLT_max.

Setting the IDLE pin to “low”, with both IN0 and IN1 also at “low” value, has the following consequences:

•

Device goes in SLEEP MODE

•

The SPI registers are reset to default value

•

in order to decrease the current consumption the voltage detection circuits on VDDIO and VBATT are

disabled.

•

SO pin remains in "HighZ" even if NCS pin is active and the SPI communication is not allowed

5.3

Reset pin (NRES, only in VFQFPN32 package option)

The NRES pin, available only for VFQFPN32 version, is the reset input for the device. The function uses the

inverse logic, if the NRES pin is low, the device is held in an internal reset state, all outputs channels are disabled,

and all registers are reset to their default values. An internal pull down will hold the NRES pin asserted in case of

pin open. As default, the state of NRES pin is masked by the logic. The user must send a specific SPI frame to

force the logic to take into account the state of NRES pin.

5.4

Enable (DIS, only in VFQFPN32 package option)

The DIS pin, available only for VFQFPN32 version, is used to enable / disable the output stages. When DIS pin is

high, all channels are disabled if the pin is not masked. An internal pull up will hold the DIS pin asserted in case of

pin open.

When DIS pin is set low, all channels are enabled based on their configuration settings. As default, the DIS pin is

masked by the logic. The user needs to send a specific SPI frame to force the logic to take into account the state

of DIS pin. The status of DIS pin can be monitored reading the STA_0 register.

The DIS pin can be connected to a general purpose output pin of the microcontroller or to an alternative safety

circuit.

5.5

SPI communications (NCS, CLK, SI & SO)

The NCS, CLK, SI & SO pins provide serial communications between the device and the microcontroller. See

Section 11: SPI for details on SPI features, device register functions and electrical characteristics.

L9026

Input/Output

DS13397 - Rev 9

page 11/60

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