L9026 datasheet(42/60 Pages) STMICROELECTRONICS

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11.5

SPI frame structure

11.5.1

MOSI frame structure

Each MOSI frame has 16 bits with the following structure:

•

1 command bit R/W, ‘1’ for write, ‘0’ for read

•

5 ADDRESS bits

•

8 DATA bits

•

1 PARITY bit, odd parity, calculated on bit [2:15]

•

1 FR_CNT frame counter bit

11.5.2

MISO frame structure

Each MISO frame has 16 bits with the following structure:

•

1 ERR error bit, ‘1’ if an error happened in the previous transmission, ‘0’ otherwise

•

5 ADDRESS bits

•

8 DATA bits

•

1 PARITY bit, odd parity, calculated on bit [2:15]

•

1 FR_CNT frame counter bit

11.6

SPI register

11.6.1

CHIP_ID

Address:

Global Base Address + 0x00

Description:

Chip ID register

Field name

Type

Bit Offset

Bit Width

Reset Value

Reset Sources

Description

CHIP_ID

AA Bit 0->7 00100010

BA Bit 0->7 00101010

BB Bit 0->7 01010101

8 bit chip identifier

CFG_0

Address:

Global Base Address + 0x01

Description:

Configuration 0

L9026

SPI

DS13397 - Rev 9

page 42/60

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