データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

IS25LE512M-RLLA3:P-TY データシート(PDF) 98 Page - Integrated Silicon Solution, Inc

部品番号 IS25LE512M-RLLA3:P-TY
部品情報  SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  189 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  ISSI [Integrated Silicon Solution, Inc]
ホームページ  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE512M-RLLA3:P-TY データシート(HTML) 98 Page - Integrated Silicon Solution, Inc

Back Button IS25LE512M-RLLA3:P-TY Datasheet HTML 94Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 95Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 96Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 97Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 98Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 99Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 100Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 101Page - Integrated Silicon Solution, Inc IS25LE512M-RLLA3:P-TY Datasheet HTML 102Page - Integrated Silicon Solution, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 98 / 189 page
background image
IS25LE512M
IS25WE512M
Integrated Silicon Solution, Inc.- www.issi.com
98
Rev. A6
06/16/2025
8.19 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into BP3, BP2, BP1, BP0, and SRWD bits. Also WRSR
instruction allows the user to di
sable or enable quad operation by writing “0” or “1” into the non-volatile QE bit.
To write Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for
the device to accept Write Status Register (01h) instruction (Status Register bit WEL must equal 1).
Figure 8.47 Write Status Register Sequence In SPI Mode
Instruction = 01h
CE #
SCK
SI
SO
Data In
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
7
3
2
1
0
6
5
4
High Impedence
Figure 8.48 Write Status Register QPI Sequence
01h
0
1
Mode 3
Mode 0
2
3
7:4
3:0
CE#
SCK
IO[3:0]
Data In



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com