L99H92 datasheet(48/77 Pages) STMICROELECTRONICS

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Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

0 = no error (default)

1 = error detected

The DE bit is cleared by a Read & Clear command of all related flags in the Status Register DSR1. The

NRDY status bit together with the CPLOW status bit (for CP_LOW_CONFIG=1) cannot be cleared by a

Read & clear command.

Global warning bit

The GW bit is a logical OR combination of warning flags. Warning bits do not lead to any device state

change or switch off of functions.

•

Thermal warning status flag (TW)

•

VS overvoltage warning status flag (VSOVW)

0 = no warning (default)

1 = warning detected

The GW bit is cleared by a Read & clear command of all related flags in the Status Register DSR1.

Fail-safe bit

The FS bit indicates that the device was forced into fail-safe mode.

•

Watchdog fault status flag (WDGF)

•

Fail-safe input not status bit (FSIN)

0 = no error (default)

1 = error detected

The FS bit is cleared by a Read & clear command of the Status register WDGF flag assuming that the FSIN

status bit is reset to zero. The FSIN status bit, logical OR of FSINLL, FSINHS1, FSINLS1, FSINHS2 and

FSINLS2, cannot be cleared by a Read & Clear command.

L99H92

Global status byte GSB

DS14069 - Rev 4

page 48/77

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