sw(max)

HS

LS

92000

F

=

Qg

+ Qg

UCD7232

www.ti.com

SLUSAH3

– MAY 2011

The logic threshold of this pin typically exhibits 450mV of hysteresis to provide noise immunity and insure

glitch-free operation of the low-side gate driver.

SRE MODE

The SRE Mode pin is a digital input designed to accept 3.3V logic levels, but is also tolerant of levels up to 5V.

This pin sets the operational mode on the device. When asserted high, the device will be placed in synchronous

mode. In this mode the behavior of both the high-side and low-side gate drive signals are under the control of the

PWM input. When asserted low, this pin configures the device for independent mode. In this mode the high-side

FET is under the control of the PWM pin. The low-side FET is under the control of the SRE pin. The SRE Mode

pin is designed to be permanently tied high or low depending on the power architecture being implemented. It is

not intended to be switched dynamically while the device is in operation. This pin can be tied to the BP3 pin to

always select synchronous mode.

VIN

VIN supplies power to the internal circuits of the device. The input power is conditioned by an internal linear

regulator that provides the VGG gate drive voltage. A second regulator that operates off of the VGG rail produces

an internal 3.3V supply that powers the internal analog and digital functional blocks. The BP3 pin provides

access for a high frequency bypass capacitor on this internal rail. The VGG regulator produces a nominal output

of 6.2V. The output of the VGG regulator is monitored by the Under-Voltage Lock-Out (UVLO) circuitry. The

device will not attempt to produce gate drive pulses until the VGG voltage is above the UVLO threshold. This

insures that there is sufficient voltage available to drive the power FETs into saturation when switching activity

begins. To use the internal VGG regulator, the voltage on Vin should be at least 4.7V.

When performing power conversion with less than 4.7V on the VIN pin, the gate drive voltage must be supplied

externally. (See VGG and VGG DIS sections for details.)

VGG

The VGG pin is the gate drive voltage for the high current gate drivers stages. The voltage on this pin can be

supplied internally by the on-chip regulator, or it can be externally supplied by the user. When using the internal

regulator, the VGG DIS pin should be tied low. When an external source of VGG is to be used, the VGG DIS pin

must be tied high. Current is drawn from the VGG supply in fast, high-current pulses. A 4.7µF ceramic capacitor

should be connected from the VGG pin to the PGND pin as close as possible to the package.

Whether internally or externally supplied, the voltage on the VGG pin is monitored by the UVLO circuitry. The

voltage must be higher than the UVLO threshold before power conversion can occur. Note that the FLT pin is

asserted high when VGG is below the UVLO threshold.

The average current drawn from the VGG supply is dependant on the switching frequency and the total gate

charge of the power FETs connected to the driver. This current can be significant and is a major contributor to

the overall power dissipation of the driver. The total gate charge (Qg) is a function of the value of VGG and the

power FET construction. A value for Qg can be obtained from the FET manufacturer

’s data sheet. A graph of Qg

vs VGS is usually supplied. Use the value of VGG as the VGS value and read the corresponding value of Qg. A

value of Qg should be obtained for both the high-side and low-side FETs.

To keep the current draw from the VGG supply within its capability, the switching frequency of the power stage

should be limited to the following:

(1)

Where Fsw(max) is the maximum switching frequency in kHz, QgHS is the gate charge of the high-side FET

measured at VGS = 6.2V, and QgLS is the total gate charge of the low-side FET(s) measured at VGS = 6.2V, both

specified in nanocoulombs (nC). Selecting FETs with lower gate charge will permit higher operating frequencies.

The formula above allows for a maximum of 92mA of total gate drive current. An additional 8mA is consumed by

the remaining circuitry within the device.

The average gate drive current, in mA, can be calculated from the following equation (with switching frequency in

kHz and charge in nC):

IGATE_AVE = (QgHS + QgLS) × Fsw × 1000

(2)

Copyright

© 2011, Texas Instruments Incorporated

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