UCD7232

www.ti.com

SLUSAH3

– MAY 2011

Digital Control Compatible Synchronous-Buck Gate Driver

With Current Sense and Fault Protection

Check for Samples: UCD7232

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FEATURES

DESCRIPTION

•

Dual High Current Drivers.

The UCD7232 high current driver is specifically

•

Full Compatibility with TI Fusion Digital Power

designed

for

digitally-controlled,

point-of-load,

Supply Controllers, such as UCD91xx and

synchronous buck switching power supplies. Two

UCD92xx Families

driver circuits provide high charge and discharge

•

Operational to 2 MHz Switching Frequency

current for the high-side NMOS switch and the

low-side

NMOS

synchronous

rectifier

in

a

•

High-Side FET and Output Current Limit

synchronous buck circuit. The MOSFET gates are

Protection with Independently Adjustable

driven by an internally regulated VGG supply. The

Thresholds

internal VGG regulator can be disabled to permit the

•

Fast High-Side Overcurrent Sense Circuit with

user to supply their own gate drive voltage. This

Fault Flag Output

– Prevents Catastrophic

flexibility allows a wide power conversion input

Current Levels on a Cycle-by-Cycle Basis

voltage range of 2.2 to 15 V. Internal under voltage

lockout (UVLO) logic insures VGG is good before

•

Differential High-Gain Current Sense Amplifier

allowing chip operation.

•

Voltage Proportional to Load Current Monitor

A drive logic block allows operation in one of two

Output

modes

selected

by

the

SRE

Mode

pin.

In

•

Wide Input Voltage Range: 4.7 V to 15 V

Synchronous Mode, the logic block uses the PWM

Operation to 2.2 V Input Supported with an

signal to control both the high-side and low-side gate

External 4.5-6.5 V Bias Supply

drive signals. Dead time is automatically adjusted to

prevent cross conduction. The Synchronous Rectifier

•

Onboard Regulated Supplies for Gate Drive

Enable (SRE) pin controls whether or not the low-side

and Internal Circuits

FET is turned on when the PWM signal is low. In

•

Integrated Thermal Shutdown

Independent Mode, the PWM and SRE pins control

•

Selectable Operation Modes:

the

high-side

and

low-side

gates

directly.

No

anti-cross-conduction logic is used in this mode.

– PWM plus Synchronous Rectifier Enable

(SRE) with Automatic Dead-Time Control

On-board comparators monitor the voltage across the

– Direct High-Gate and Low-Gate Inputs for

high side switch and the voltage across an external

Direct FET Control

current sense element to safeguard the power stage

from sudden high current loads. Blanking delay is set

•

3-State PWM Input for Power Stage Shutdown

for the high side comparator by a single resistor in

•

UVLO Housekeeping Circuit

order to avoid false reports coincident with switching

•

Rated from

–40°C to +125°C Junction

edge noise. In the event of a high-side fault or an

Temperature

over-current fault, the high-side FET turned off and

the Fault Flag (FLT) is asserted to alert the digital

controller. The fault thresholds are independently set

APPLICATIONS

by the HS Sense and ILIM pins.

•

Digitally-Controlled Synchronous-Buck Power

Output current is measured and monitored by a

Stages for Single- and Multi-Phase

precision, high gain, switched capacitor differential

Applications

amplifier that processes the voltage present across

•

Digitally-Controlled Power Modules

an external current sense element. The amplified

signal is available for use by the digital controller on

the IMON pin. The current sense amplifier has output

offset of 0.5 V so that both positive (sourcing) and

negative (sinking) current can be sensed.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright

© 2011, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.