PWM

FLT

HS

Gate

LS

Gate

FaultDetected

UCD7232

SLUSAH3

– MAY 2011

www.ti.com

FLT

The Fault Flag (FLT) is a digital output pin that is asserted when a significant fault is detected. It is meant to alert

the host controller to an event that has interrupted power conversion. The FLT pin is held low in normal

operation. When a fault is detected it is asserted high (3.3V). There are four events that can trigger the FLT

signal: output over-current, high-side over-current, UVLO and thermal shutdown. The operation of the device

during fault conditions is described in the Fault Behavior section. When asserted in response to an over-current

fault, the FLT signal is reset low upon the falling edge of a subsequent PWM pulse, provided no faults are

detected during the on-time of the pulse. If the fault is still present, the flag will remain asserted. When asserted

in response to an UVLO or thermal shutdown event, the FLT pin will automatically de-assert itself when the

UVLO or thermal event has passed. If the on-time of the PWM pulse is less than 100ns, then more than one

pulse may be required to reset the flag.

BP3

The BP3 pin provides a connection point for a bypass capacitor that quiets the internal 3.3V voltage rail. Connect

a 1

µF (or greater) ceramic capacitor from this pin to analog ground. Do not draw current from this pin. It is not

intended to be a significant source of 3.3V. It can, however, be used to as a source of 3.3V for an ILIM voltage

divider and a tie point for the SRE Mode pin. Current draw should be limited to 100

µA or less.

FAULT BEHAVIOR

When faults are detected, the device reacts immediately to minimize power dissipation in the FETs and protect

the system. The type of fault influences the behavior of the gate drive signals.

When a thermal shutdown fault occurs, both HS Gate and LS Gate are immediately forced low. They will stay

low, regardless of the state of PWM and SRE, for the duration of the thermal shutdown.

A UVLO fault occurs when the voltage on the VGG pin is less than the UVLO threshold. During this time both the

HS Gate and LS Gate are driven low, regardless of the state of PWM and SRE. The fault is automatically cleared

when the VGG voltage rises above the UVLO threshold.

When either a high-side fault or an output over-current fault is detected, the FLT pin is asserted high, and both

gate signals are immediately pulled low. During a high-side fault, a high-side gate pulse will be issued with each

incoming PWM pulse. If the fault is still present, the HS Gate signal will again be truncated. This behavior

repeats on a cycle-by-cycle basis until the fault is gone or the PWM input is held low. This behavior is illustrated

in Figure 5.

Figure 5. High-Side Over-Current Fault Response

When a high-side fault and output over-current fault are detected concurrently, then both FET drives are

immediately turned off and held off. If the output over-current fault is still present at the next PWM rising edge,

then no HS Gate pulse will be issued and both gates will continue to be held off. Unlike the high-side fault

detection circuitry, the output over-current fault circuitry is not reset on a cycle-by-cycle basis. The output current

must fall below the over-current threshold before switching will resume.

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Copyright

© 2011, Texas Instruments Incorporated