M7010R datasheet(31/67 Pages) STMICROELECTRONICS

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M7010R

Table 21. READ Address Format for Data and Mask Arrays

WRITE COMMAND

TheWRITE canbea singlewrite of adata array,

mask array, register, or external SRAM location

(CMD[2] = 0). It can also be a burst WRITE

(CMD[2] = 1) using an internal auto-incrementing

address register (WBURADR) of the data array or

mask array locations (see Table 23, page 33 for

format). A single-location WRITE is a three-cycle

operation, shown in Figure 22, page 32. The burst

WRITE adds one extra cycle for each successive

location write.

The WRITE operation sequence is as follows:

– Cycle 1A: The host ASIC applies the WRITE In-

structiontoCMD[1:0] (CMD[2] = 0), usingCM-

DV=1 and the address supplied on the DQ Bus,

as shown in Table 22, page 33. The host ASIC

also supplies the index to the global mask reg-

ister (GMR) to mask the WRITE to the data ar-

rayormaskarraylocation in CMD[5:3]. For

SRAM writes, the host ASIC must supply

SADR[21:19] on CMD[8:6].

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction to CMD[1:0] (CMD[2] = 0)

using CMDV = 1 and the address supplied on

the DQ Bus. The host ASIC continues to supply

the GMR Index to mask the WRITE to the data

or mask array locations in CMD[5:3]. The host

ASIC selects the device where ID[4:0] matches

the DQ[25:21] = 11111.

– Cycle 2: The host ASIC drives the DQ[67:0]

with the data to be written to the data array,

mask array, external SRAM, or register location

of the selected device.

– Cycle 3: Idle cycle. At the termination of this cy-

cle, another operation can begin.

The burst WRITE operation lasts for (n + 2) CLK

cycles, where “n” signifies the number of accesses

in the burst as specified in the BLEN field of the

WBURREG register (see Figure 23, page 32).

This operation assumes that the host ASIC has

programmed the WBURREG with the starting ad-

dress (ADDR) and the length of transfer (BLEN)

before initiating the burst WRITE command (see

Table 24, page 33 for format). The sequence is as

follows:

– Cycle 1A: The host ASIC applies the WRITE In-

struction on the CMD[1:0] (CMD[2] = 1), using

CMDV = 1 and the address supplied on the DQ

Bus, as shown in Table 23, page 33. The host

ASIC also supplies the index to the global mask

array locations in CMD[5:3].

– Cycle 1B: The host ASIC continues to apply the

WRITE Instruction to CMD[1:0] (CMD[2] = 0)

using CMDV = 1 and the address supplied on

the DQ Bus. The host ASIC continues to supply

the GMR Index to mask the WRITE to the data

or mask array locations in CMD[5:3]. The host

ASIC selects the device where ID[4:0] matches

the DQ[25:21] = 11111.

– Cycle 2: The host ASIC drives the DQ[67:0]

with thedatatobewritten to thedataarray or

mask array location of the selected device. The

host ASIC writes the data on the DQ[67:0] bus

only to the subfield that has the corresponding

mask bit set to '1' in the global mask register

specified by the index CMD[5:3] and supplied in

Cycle 1.

– Cycles 3 to n + 1: The host ASIC drives

DQ[67:0] with the data to be written to the next

data array or mask array location (addressed by

the auto-increment AADR field of the WBUR-

REG register) of the selected device.

The host ASIC writes the data on the DQ[67:0]

bus only to the subfield that has the correspond-

ing mask bit set to '1' in the global mask register

specified by the index CMD[5:3] and supplied in

Cycle 1. The M7010R drives the EOT signal low

from Cycle 3 to Cycle n; the M7010R drives the

EOT signal highinCycle n+1(nis specifiedin

the BLEN field of the WBURREG).

– Cycle n + 2: The M7010R drives the EOT signal

low. At the termination of the Cycle n + 2, the

M7010R floats the EOT signal to a 3-state, and

a new instruction can begin.

DQ[67:26]

DQ[25:21]

DQ[20:19]

DQ[18:14]

DQ[13:0]

Reserved

00: Data Array

Reserved

Do not care. These 14 bits come from the

internal register (RBURADR) which

increments for each access.

Reserved

01: Mask Array

Reserved

Do not care. These 14 bits come from the

internal register (RBURADR) which

increments for each access.

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