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AS3418

Functional Description

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

│ 45

Figure 63:

Current Address Read

To keep the access time as short as possible, this format allows a read access without the word

address transfer in advance to the data transfer. The bus is idle and the master issues a START

condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is

terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an

unlimited number of data bytes can be transferred, where the data bytes have to be responded with an

acknowledge from the master. For termination of the transmission, the master sends a not-

acknowledge following the last data byte and a subsequent STOP condition.

6.12.2

Parameter

VBAT =1.8V, TA=25ºC, unless otherwise specified.

Figure 64:

2C Serial Timing

Figure 65:

2C Serial Interface Parameter

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCSL

CSCL, CSDA Low

Input Level

(max 30% VBAT)

0.42

VCSH

CSCL, CSDA High

Input Level

CSCL, CSDA (min 70% VBAT)

1.16

HYST

CSCL, CSDA Input

Hysteresis

450

reg_data n

data

reg_data 2

...

RA++

1-7

ANC/CSDA

MODE/CSCL

1-7

Start

Condition

Address

R/W

ACK

Data

ACK

Data

ACK

Stop

Condition

TSU

T HD

TPD

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