EM88F758NL44 datasheet(6/190 Pages) EMC

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Contents



Product Specification (V1.1) 03.25.2016

6.1.118 Bank 2 RC TPCR3 (Touch Key Control Register 3) .......................................76

6.1.119 Bank 2 RD TPAHTH (Most Significant Byte of Group A

High Wakeup Threshold) ................................................................................77

6.1.120 Bank 2 RE TPAHTL (Least Significant Byte of Group A

High Wakeup Threshold) ................................................................................77

6.1.121 Bank 2 RF TPALTH (Most Significant Byte of Group A

Lower Wakeup Threshold)..............................................................................77

6.1.122 Bank 2 R10 TPALTL (Least Significant Byte

of Group A Lower Wakeup Threshold)........................................................... 77

6.1.123 Bank 2 R11 TPBHTH (Most Significant Byte of Group B

High Wake-up Threshold) ...............................................................................78

6.1.124 Bank 2 R12 TPBHTL (Least Significant Byte of Group B

High Wakeup Threshold) ................................................................................78

6.1.125 Bank 2 R13 TPBLTH (Most Significant Byte of Group B

Lower Wakeup Threshold)..............................................................................78

6.1.126 Bank 2 R14 TPBLTL (Least Significant Byte of Group B

Lower Wakeup Threshold)..............................................................................78

6.1.127 Bank 2 R15 TPAH (Most Significant Byte of A Group Touch Key Buffer) .......79

6.1.128 Bank 2 R16 TPAL (Least Significant Byte of A Group Touch Key Buffer).......79

6.1.129 Bank 2 R17 TPBH (Most Significant Byte of B Group Touch Key Buffer) ......79

6.1.130 Bank 2 R18 TPBL (Least Significant Byte of B Group Touch Key Buffer) ......79

6.1.131 Bank 2 R19 TPSTH (Most Significant Byte of Sense Time) ...........................79

6.1.132 Bank 2 R1A TPSTL (Least Significant Byte of Sense Time) ..........................80

6.1.133 Bank 2 R1B~R46: (Reserved) ........................................................................80

6.1.134 Bank 2 R47 LOCKPR (Lock Page Number Register) ....................................80

6.1.135 Bank 2 R48 LOCKCR (Lock Control Register) ...............................................80

6.1.136 R50~R7F, Banks 0~3 R80~RFF.....................................................................80

6.2 TCC/WDT and Prescaler ................................................................................ 81

6.3 I/O Ports ......................................................................................................... 83

6.4 Reset and Wake-up ........................................................................................ 87

6.4.1

Reset...............................................................................................................87

6.4.2

Status of RST, T, and P of Status Register .....................................................91

6.5 Interrupt........................................................................................................ 112

6.6 Touch Key..................................................................................................... 114

6.6.1

Overview .......................................................................................................115

6.6.2

Function Description .....................................................................................115

6.6.3

Normal Mode Programming..........................................................................116

6.7 A/D Converter............................................................................................... 117

6.7.1

ADC Data Register .......................................................................................118

6.7.2

A/D Sampling Time .......................................................................................118

6.7.3

A/D Conversion Time....................................................................................119

6.7.4

ADC Operation during Sleep Mode ..............................................................119

6.7.5

Programming Process/Considerations .........................................................120

6.7.6

Programming Process for Detecting Internal VDD .......................................120

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