RZSLASHG2UL datasheet(2/67 Pages) RENESAS

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RZ/G2UL Group

1. Overview

R01DS0486EJ0110 Rev.1.10

Page 2 of 67

Jun 16, 2025

Overview

1.1

Outline of Specification

1.1.1

CPU Core

Item

Description

System CPU Cortex-A55

[RZ/G2UL (Type-1) RZ/G2UL (Type-2)]

● Arm Cortex-A55 Single MPCore 1.0 GHz

● L1 I-cache 32 Kbytes (Parity) / D-cache 32 Kbytes (ECC)

● L2 cache 0 Kbyte

● L3 cache 256 Kbytes (ECC)

● Arm® NEON™ / FPU supported

● Cryptographic Extension supported

● Arm® v8.2-A architecture

System CPU Cortex-M33

[RZ/G2UL (Type-1) RZ/G2UL (Type-2)]

● Arm Cortex-M33 Processor 200 MHz

● Security Extension supported

● Arm® v8-M architecture

Boot

[RZ/G2UL (Type-1) RZ/G2UL (Type-2)]

● 6 boot modes

Boot Mode 0: Booting from eSD

Boot Mode 1: Booting from eMMC (1.8 V)

Boot Mode 2: Booting from eMMC (3.3 V)

Boot Mode 3: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi

I/O bus space (1.8 V)

Boot Mode 4: Booting from a serial flash memory (Single / Quad) connected to the SPI Multi

I/O bus space (3.3 V)

Boot Mode 5: Booting from SCIF download

Debug Interface

[RZ/G2UL (Type-1) RZ/G2UL (Type-2)]

● Arm® CoreSight™ architecture

● JTAG / SWD interface supported

● ETF 16 Kbytes for program flow trace (each cluster)

● JTAG Disable supported

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