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RZ/T2ME データシート(PDF) 43 Page - Renesas Technology Corp |
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RZ/T2ME データシート(HTML) 43 Page - Renesas Technology Corp |
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43 / 116 page  Table 2.11 Permissible Output Currents Item Symbol Conditions Min. Typ. Max. Unit Permissible output low current (max. value per pin) IOL All output pins — — 12 mA Permissible output low current (total) ΣIOL Sum of all output pins — — 80 mA Permissible output high current (max. value per pin) IOH All output pins — — -12 mA Permissible output high current (total) ΣIOH Sum of all output pins — — -80 mA Note: All output current values shall be within the values in this table to ensure the reliability of this LSI. Table 2.12 Thermal Resistance value (Reference) Item Symbol Package Max. Unit Thermal Resistance Θja 320 pin FBGA 17 × 17 mm, 0.8-mm pitch 25.0 °C/W 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 25.3 °C/W Ψjt 320 pin FBGA 17 × 17 mm, 0.8-mm pitch 0.30 °C/W 225 pin FBGA 13 × 13 mm, 0.8-mm pitch 0.31 °C/W Note: Package thermal resistance values above are based on EIA/JESD51-9 (2s2p) condition and reference only. 2.5 AC Characteristics Table 2.13 Operating frequency Parameter Symbol Min. Max. Unit Operating frequency CPU clock (CPUnCLK, n = 0, 1) f 150 200 600 800 MHz System clock (ICLK) 150 200 Peripheral module clock H (PCLKH) 150 200 Peripheral module clock M (PCLKM) 75 100 Peripheral module clock L (PCLKL) 37.5 50 Peripheral module clock for ADC (PCLKADC) 18.75 25 Peripheral module clock for SCIn (PCLKSCIn, n = 0 to 5) 75 100 Peripheral module clock for SPIn (PCLKSPIn, n = 0 to 3) 75 100 External bus clock output (CKIO) 18.75 100 Ethernet PHY reference clock (ETHn_REFCLK, n = 0 to 2) 25 Ethernet PHY reference clock (RMIIn_REFCLK, n = 0 to 2) 50 AC Characteristics are defined in condition of the IO setting (DRCTLm register setting) show in Table 2.14. Table 2.14 IO setting (DRCTLm register setting) condition (1 of 2) Module Signal IO type Voltage DRCTLm register DRVn SRn SMTn Bus CKIO SDRAM and High drive — 3.3 V High Fast — Other than the above — 3.3 V Middle Fast — Other than the above Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable DMAC, MTU3, IIC, CANFD, DSMIF All signals Type A 3.3 V Middle Slow Disable Type B 3.3 V Low Slow Disable RZ/T2ME Datasheet 2. Electrical Characteristics R01DS0441EJ0110 Rev.1.10 Mar 13, 2026 Page 43 of 116 |
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