RZSLASHT2ME datasheet(2/116 Pages) RENESAS

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Overview

1.1

Outline of Specifications

The MPU is a high-performance ASSP that has dual Arm Cortex®-R52 processor with Floating-Point Unit (FPU) and

NEON™. It incorporates integrated peripheral functions necessary for system configuration.

Table 1.1

CPU

Feature

Functional description

Arm® Cortex®-R52

● Two processors consist of single core

● Operating frequency

– 200 MHz/400 MHz/800 MHz (in case of 200 MHz system clock)

– 150 MHz/300 MHz/600 MHz (in case of 150 MHz system clock)

● 32-bit CPU Cortex-R52 designed by Arm (core revision r1p2)

● Address space: 4 GB

● Instruction cache

– CPU0: 16 KB (with ECC)

– CPU1: 32 KB (with ECC)

● Data cache

– CPU0: 16 KB (with ECC)

– CPU1: 32 KB (with ECC)

● Tightly coupled memory (TCM)

– CPU0

ATCM: 512 KB (with ECC) 1 wait (0 wait selectable if less than 400 MHz)

BTCM: 64 KB (with ECC) 0 wait

CTCM: 0 KB (with ECC)

– CPU1

ATCM: 0 KB

BTCM: 0 KB

CTCM: 0 KB

● Instruction set: Arm v8-R architecture, so support includes Thumb® and Thumb-2

● Data arrangement

– Instructions: Little endian

– Data: Little endian

● 2-stage memory protection unit (MPU)

● No DCLS (Dual Core Lock Step) support

FPU

● Supports addition, subtraction, multiplication, division, multiply-and-accumulate, and

square-root operations at single- and double-precision.

● Registers

64-bit single-word registers: 64 bits × 32

(can be used as 16 double-word registers: 128 bits × 16)

NEON

The Advanced SIMD supporting integer or single precision results

Table 1.2

Memory

Feature

Functional description

On-chip system SRAM with ECC

● Capacity: Up to 2.0 MB (512 KB × 4 units) (with ECC)

● Operating frequency: 150 MHz/200 MHz

● SEC-DED (single error correction/double error detection)

Error injection supported

One-time programmable memory

● Overwrite protection

● Redundancy support

● ECC support

● Available information

– Unique ID

– Authentication settings

– Trimming data

– Boot mode setting

– User area

RZ/T2ME Datasheet

1. Overview

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

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