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ST10R272L データシート(PDF) 59 Page - STMicroelectronics

部品番号 ST10R272L
部品情報  16-BIT LOW VOLTAGE ROMLESS MCU WITH MAC
PDF  77 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10R272L データシート(HTML) 59 Page - STMicroelectronics

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ST10R272L - ELECTRICAL CHARACTERISTICS
16.3.4
Demultiplexed Bus
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40 to +85 °C
CL = 50 pF
ALE cycle time = 4 TCL + 2
tA + tC + tF (40 ns at 50 MHz CPU clock without waitstates)
Parameter
Symbol
Max CPU Clock 50MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
min.
max.
min.
max.
ALE high time
t5
CC
7 +
tA
–
TCL - 3 +
tA
–ns
Address (P1, P4), BHE
setup to ALE
t6
CC
3 +
tA
–
TCL - 7 +
tA
–ns
Address setup to RD, WR
(with RW-delay)
t80
CC
13 +
2tA
–
2TCL - 7 +
2tA –ns
Address setup to RD, WR
(no RW-delay)
t81
CC
3 +
2tA
–
TCL - 7 +
2tA –ns
RD, WR low time
(with RW-delay)
t12
CC
13 +
tC
–
2TCL - 7 +
tC –ns
RD, WR low time
(no RW-delay)
t13
CC
23 +
tC
–
3TCL - 7 +
tC –ns
RD to valid data in
(with RW-delay)
t14
SR
–
5 +
tC
–
2TCL - 15
+
tC
ns
RD to valid data in
(no RW-delay)
t15
SR
–
15 +
tC
–
3TCL - 15
+
tC
ns
ALE low to valid data in
t16
SR
–
15 +
tA + tC –
3TCL - 15
+
tA + tC
ns
Address to valid data in
t17
SR
–
20 + 2
tA +
tC
–
4TCL - 20
+ 2
tA + tC
ns
Data hold after RD
rising edge
t18
SR
0
–
0
–
ns
Data float after RD rising
edge (with RW-delay)1) 2)
t20
SR
–
15
+
tF + 2tA
2
–2TCL - 5
+
tF + 2tA
2
ns
Data float after RD rising
edge (no RW-delay)1 2
t21
SR
–
5 +
tF +
2
tA
2
–TCL - 5
+
tF + 2tA
2
ns
Data valid to WR
t22
CC
13 +
tC
–
2TCL - 7 +
tC –ns
Table 18 Demultiplexed bus
1



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