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ST18952 データシート(PDF) 18 Page - STMicroelectronics

部品番号 ST18952
部品情報  DIGITAL SIGNAL PROCESSOR DSP CHIP
PDF  67 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST18952 データシート(HTML) 18 Page - STMicroelectronics

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ST18952
6
Bus Switch Unit
The three memory spaces can be extended off-chip through the bus switch unit (BSU)
peripheral. The figure below shows the layout of the D950Core BSU.
Figure 6.1
D950Core Bus Switch Unit
6.1
BSU operation
The BSU recognizes a bus cycle when a bus extension strobe (IBSE, XBSE or YBSE) goes
active. The BSU decodes the address value to determine if an external memory access is
requested on the I, X or Y-bus and generates the appropriate signals on the external bus side.
The BSU generates software wait-states, depending on the setting of the control register.
If more than one external memory access is attempted at one instruction cycle, they are
serviced sequentially in the following order: I-bus, X-bus, Y-bus.
Each external access requires one basic instruction clock cycle (2 CLKIN cycles), extended
by, at least, one wait-state (2 CLKIN cycles). The number of wait-states can be extended,
either by software with the BSU control registers (see Section 6.2), or by hardware with the
DTACK input signal.
EA
ED
ID
IA
YD
YA
XA
XD
D950Core
BUS
SWITCH
UNIT
DTACK
AS-DSP
BSU_CLK
RESET
IRD/XRD/YRD
IWR/XWR/YWR
IBS/XBS/YBS
16
16
16
16
INTERNAL MEMORI ES
& PERIPHERALS
16
16
16
16
P
MEM.
X
MEM.
Y
MEM.
22
2
DTACKin
EYRD/DS
EYWR/RD
EIRD/DS
EIWR/RD
EXRD/DS
EXWR/RD
VR02020A
INTERNAL MEMORIES
& PERIPHERALS
INTERNAL MEMORIES
& PERIPHERALS
DEID/DEXD/DEYD
IID/I XD/IYD
IDT_EN



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