ST72411R datasheet(33/71 Pages) STMICROELECTRONICS

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ST72411R

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MISCELLANEOUS REGISTER (Cont’d)

0 ,6 &( / / $ 1 ( 2 8 6 5 ( *,67 ( 5

0 ,6&5

Read/Write

Reset Value: x000 0000 (x0h)

(for bit 7, the reset value depends on VDD)

Bit 7 = PSSF

Power Supply Supervisor Flag

This bit is set and cleared by hardware.

0: VDD is greater than VPSS.

1: VDD is less than VPSS.

Bit 6= LVD

LVD ON during HALT mode

This bit is set and cleared by software.

This bit is used to keep the LVD active during

HALT mode.

0: LVD switched off in HALT mode (reset state).

1: LVD active in HALT mode.

Bit 5 = IPB

Interrupt polarity for port B

This bit is used to reverse the external interrupt

sensitivity polarity of the port B[6:0] pins. It is set

and cleared by software.

0: Standard sensitivity polarity

1: Reversed sensitivity polarity

Note: See IS[1:0] bit description for more details.

This bit can be written only when the I bit of the CC

Bit 4:3 = IS[1:0]

EI0 and EI1 sensitivity

These bits are used to program the interrupt sen-

sitivity of the following external interrupts:

- EI1 (port B[6:0])

- EI0 (port A[7:0])

These 2 bits can be written only when the I bit of

the CC register is set to 1 (interrupt masked).

Bit 2 = PDIE

Power Down Interrupt Enable

This bit is set and cleared by software.

0: Power down interrupt disabled

1: Power down interrupt enabled

Bit 1 = PDF

Power Down Flag

This bit is set and cleared by software or set by

hardware if (VREF -VDD) > M. If the PDIE bit is set,

an interrupt is generated when PDF is set (sensi-

tivity is high level). It can be cleared only by soft-

ware writing zero. It can also be set by software,

generating an interrupt if PDIE is enabled.

0: (VREF -VDD) < M : No open VDD circuit detected

1: (VREF -VDD) > M : Open VDD circuit detected.

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC /2

1: Slow mode. fCPU = fOSC /32

See low power mode and MCC chapters for more

details.

654

210

PSSF LVD

IPB

IS1

IS0

PDIE

PDF

SMS

IS1

IS0

External Interrupt Sensitivity

MISCR.IPB=0

MISCR.IPB=1

Falling edge &

low level

Rising edge

& high level

Rising edge only

Falling edge only

Rising edge only

Rising and falling edge

IS1

IS0

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

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