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ADE7566/ADE7569

Preliminary Technical Data

Rev. PrA | Page 54 of 136

Watt Absolute Accumulation Mode

The ADE7566/ADE7569 are placed in watt absolute accumula-

tion mode by setting the ABSAM bit in the ACCMODE Register

(0x0F). In this mode, the energy accumulation is done using the

absolute active power, ignoring any occurrence of power below

the no-load threshold (see Figure 55). The CF pulse also reflects

this accumulation method when in this mode. The default

setting for this mode is off. Detection of the transitions in the

direction of power flow, and detection of no-load threshold are

active in this mode.

POS

INTERRUPT STATUS REGISTERS

NEG

APSIGN FLAG

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

ACTIVE ENERGY

APNOLOAD

Figure 55. Energy Accumulation in Absolute Accumulation Mode

Active Energy Pulse Output

All of the ADE7566/ADE7569 circuitry has a pulse output whose

frequency is proportional to active power (see the Active Power

Calculation section). This pulse frequency output uses the

calibrated signal from the WGAIN register output, and its

behavior is consistent with the setting of the active energy

accumulation mode in the ACCMODE Register (0x0F). The

pulse output is active low and should be preferably connected to

an LED as shown in Figure 66.

Line Cycle Active Energy Accumulation Mode

In line cycle active energy accumulation mode, the energy accumu-

lation of the ADE7566/ADE7569 can be synchronized to the

voltage channel zero crossing so that active energy can be

accumulated over an integral number of half-line cycles. The

advantage of summing the active energy over an integer number

of line cycles is that the sinusoidal component in the active energy

is reduced to 0. This eliminates any ripple in the energy calculation.

Energy is calculated more accurately and more quickly because

the integration period can be shortened. By using this mode,

the energy calibration can be greatly simplified, and the time

required to calibrate the meter can be significantly reduced.

In the line cycle active energy accumulation mode, the

ADE7566/ADE7569 accumulate the active power signal in the

LWATTHR register for an integral number of line cycles, as shown

in Figure 56. The number of half-line cycles is specified in the

LINCYC register.

The ADE7566/ADE7569 can accumulate active power for up to

65,535 half-line cycles. Because the active power is integrated

on an integral number of line cycles, the CYCEND flag in the

Interrupt Status Register 3 SFR (MIRQSTH, 0xDE) is set at the

end of an active energy accumulation line cycle. If the CYCEND

enable bit in the Interrupt Enable Register 3 SFR (MIRQENH,

0xDB) is set, the 8052 core has a pending ADE interrupt. The

ADE interrupt stays active until the CYCEND status bit is

cleared (see the Energy Measurement Interrupts section).

Another calibration cycle starts as soon as the CYCEND flag is

set. If the LWATTHR register is not read before a new CYCEND

flag is set, the LWATTHR register is overwritten by a new value.

WDIV[7:0]

WATTOS[15:0]

WGAIN[11:0]

LPF1

LWATTHR [23:0]

ACCUMULATE

ACTIVE ENERGY IN

INTERNAL REGISTER

AND UPDATE THE

LWATTHR REGISTER

AT THE END OF LINCYC

HALF LINE CYCLES

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL

ADC

LINCYC [15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

DIGITAL-TO-FREQUENCY

CONVERTER

Figure 56. Line Cycle Active Energy Accumulation

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