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ADE7566 データシート(PDF) 88 Page - Analog Devices |
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ADE7566 データシート(HTML) 88 Page - Analog Devices |
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88 / 136 page  ADE7566/ADE7569 Preliminary Technical Data Rev. PrA | Page 88 of 136 Table 75. LCD Configuration X SFR (LCDCONX, 0x9C) Bit No. Mnemonic Default Description 7 Reserved 0 Reserved. External Resistor Ladder Selection Bit. EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 6 EXTRES 0 1 External resistor ladder is enabled. Charge pump is disabled. 5 to 0 BIASLVL[5:0] 0 Bias Level Selection Bits. See Table 76. Table 76. LCD Bias Voltage When Contrast Control Is Enabled 1/2 Bias 1/3 Bias BIASLVL[5] VA (V) VB VC VB VC 0 [] 31 4:0 BLVL V REF × VB = VA VC = 2 x VA VB = 2 x VA VC = 3 x VA 1 [] ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + × 31 1 4:0 BLVL V REF VB = VA VC = 2 x VA VB = 2 x VA VC = 3 x VA Table 77. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit No. Mnemonic Default Description 7 Reserved 0 This bit should be kept cleared for proper operation. 6 INV_LVL 0 Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this bit is cleared, frames are not inverted. 5 to 2 Reserved 0 These bits should be kept cleared for proper operation. 1 UPDATEOVER 0 Update Finished Flag Bit. This bit is updated by LCD driver. When set, this bit indicates that the LCD memory has been updated and a new frame has begun. 0 REFRESH 0 Refresh LCD Data Memory Bit. This bit should be set by user. When set, the LCD driver does not use the data in the LCD data registers to update display. The LCD data registers can be updated by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display at the next frame. Table 78. LCD Clock SFR (LCDCLK, 0x96) Bit No. Mnemonic Default Description Blink Mode Clock Source Configuration Bits. BLKMOD[1:0] Result 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 10 The blink rate is 2 Hz 7 to 6 BLKMOD[1:0] 0 11 The blink rate is set by BLKFREQ[1:0] Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11 BLKFREQ[1:0] Result (Blink Rate) 00 1 Hz 01 1/2 Hz 10 1/3 Hz 5 to 4 BLKFREQ[1:0] 0 11 1/4 Hz 3 to 0 FD[3:0] 0 LCD Frame Rate Selection Bits. See Table 79 and Table 80. |
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