STLC5466 datasheet(4/130 Pages) STMICROELECTRONICS

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STLC5466

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VI.4

INPUT MULTIPLEX CONFIGURATION REGISTER 1 ........... IMCR1 (06)H.......................34

VI.5

OUTPUT MULTIPLEX CONFIGURATION REGISTER 0........ OMCR0 (08)H.....................34

VI.6

OUTPUT MULTIPLEX CONFIGURATION REGISTER 1........ OMCR1 (0A)H ....................34

VI.7

SWITCHING MATRIX CONFIGURATION REGISTER ........... SMCR (0C)H.......................35

VI.8

CONNECTION MEMORY DATA REGISTER ......................... CMDR (0E)H.......................37

VI.9

CONNECTION MEMORY ADDRESS REGISTER ................. CMAR (10)H .......................41

VI.10

SEQUENCE FAULT COUNTER REGISTER ......................... SFCR (12)H ........................45

VI.11

TIME SLOT ASSIGNER ADDRESS REGISTER 1.................. TAAR1 (14)H ......................45

VI.12

TIME SLOT ASSIGNER DATA REGISTER 1 ......................... TADR1 (16)H ......................45

VI.13

HDLC TRANSMIT COMMAND REGISTER 1 ......................... HTCR1 (18)H......................46

VI.14

HDLC RECEIVE COMMAND REGISTER 1 ............................ HRCR1 (1A)H .....................48

VI.15

ADDRESS FIELD RECOGNITION ADDRESS REGISTER 1 . AFRAR1 (1C)H ...................50

VI.16

ADDRESS FIELD RECOGNITION DATA REGISTER 1 ......... AFRDR1 (1E)H ...................50

VI.17

FILL CHARACTER REGISTER 1 ............................................ FCR1 (20)H ........................51

VI.18

GCI CHANNELS DEFINITION REGISTER 0 ......................... GCIR0 (22)H.......................51

VI.19

GCI CHANNELS DEFINITION REGISTER 1 .......................... GCIR1 (24)H.......................51

VI.20

GCI CHANNELS DEFINITION REGISTER 2 .......................... GCIR2 (26)H.......................52

VI.21

GCI CHANNELS DEFINITION REGISTER 3 .......................... GCIR3 (28)H.......................52

VI.22

TRANSMIT COMMAND / INDICATE REGISTER .................. TCIR (2A)H .........................52

VI.23

TRANSMIT MONITOR ADDRESS REGISTER....................... TMAR (2C)H .......................53

VI.24

TRANSMIT MONITOR DATA REGISTER .............................. TMDR (2E)H .......................54

VI.25

TRANSMIT MONITOR INTERRUPT REGISTER.................... TMIR (30)H .........................55

VI.26

MEMORY INTERFACE CONFIGURATION REGISTER ......... MICR (32)H.........................55

VI.27

INITIATE BLOCK ADDRESS REGISTER 1 ........................... IBAR1 (34)H .......................56

VI.28

INTERRUPT QUEUE SIZE REGISTER ................................. IQSR (36)H .........................56

VI.29

INTERRUPT REGISTER ........................................................ IR (38)H ..............................57

VI.30

INTERRUPT MASK REGISTER.............................................. IMR (3A)H...........................58

VI.31

TIMER REGISTER 1 ............................................................... TIMR1 (3C)H ......................59

VI.32

TEST REGISTER .................................................................... TR (3E)H.............................59

VI.33

GENERAL CONFIGURATION REGISTER 2 .......................... GCR2 (42)H........................60

VI.34

SPLIT FETCH MEMORY REGISTER ..................................... SFMR (4E)H .......................61

VI.35

TIME SLOT ASSIGNER ADDRESS REGISTER 2.................. TAAR2 (54)H ......................62

VI.36

TIME SLOT ASSIGNER DATA REGISTER 2 ......................... TADR2 (56)H ......................62

VI.37

HDLC TRANSMIT COMMAND REGISTER 2 ........................ HTCR2 (58)H......................63

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