TDA7580 datasheet(27/39 Pages) STMICROELECTRONICS

27 / 39 page

TDA7580

I2C timing

27/39

I2C timing

Figure 16.

DSP and RDS I2C BUS timings

Table 21.

I2C BUS timing table

(Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V)

Symbol

Parameter

Test

condition

Standard mode

I2C BUS

Fast mode

I2C BUS

Unit

Min.

Max.

Min.

Max.

FSCL

SCLl clock frequency

100

400

kHz

tBUF

Bus free between a stop and start

condition

4800

–

1300

–

tHD:STA

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

4800

–

600

–

tLOW

LOW period of the SCL clock

4800

–

1300

–

tHIGH

HIGH period of the SCL clock

4800

–

600

–

tSU:STA

Set-up time for a repeated start

condition

4800

–

600

–

tHD:DAT

DATA hold time

900

Rise time of both SDA and SCL signals

Cb in pF

–

300

12+0.1Cb

300

Fall time of both SDA and SCL signals

Cb in pF

–

300

12+0.1Cb

300

tSU;STO Set-up time for STOP condition

4800

–

600

–

tSU:DAT

Data set-up time

250

–

250

–

Capacitive load for each bus line

400

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