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PSD835G2-70UI データシート(PDF) 84 Page - STMicroelectronics

部品番号 PSD835G2-70UI
部品情報  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2-70UI データシート(HTML) 84 Page - STMicroelectronics

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PSD835G2
PSD8XX Family
83
-70
-90
Turbo
Symbol
Parameter
Conditions
Min
Max
Min
Max
Off
Unit
tAVQV (PF)
Address Valid to Data Valid
(Note 3)
30
35
Add 12
ns
tSLQV (PF)
CSI Valid to Data Valid
25
35
Add 12
ns
RD to Data Valid
(Notes 1 and 4)
21
32
ns
tRLQV (PF)
RD to Data Valid 8031 Mode
31
38
ns
tDVQV (PF)
Data In to Data Out Valid
22
30
ns
tQXRH (PF)
RD Data Hold Time
0
0
ns
tRLRH (PF)
RD Pulse Width
(Note 1)
27
32
ns
tRHQZ (PF)
RD to Data High-Z
(Note 1)
23
25
ns
Port F Peripheral Data Mode Read Timing (5 V ± 10%)
-70
-90
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tWLQV (PF)
WR to Data Propagation Delay
(Note 2)
25
35
ns
tDVQV (PF)
Data to Port F Data Propagation Delay
(Note 5)
22
30
ns
tWHQZ (PF)
WR Invalid to Port F Tri-state
(Note 2)
20
25
ns
Port F Peripheral Data Mode Write Timing (5 V ± 10%)
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. WR timing has the same timing as E and DS signals.
3. Any input used to select Port F Data Peripheral Mode.
4. Data is already stable on Port F.
5. Data stable on ADIO pins to data on Port F.
Microcontroller Interface – PSD835G2 AC/DC Parameters
(5V ± 10% Versions)



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