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PSD835G2-70UI データシート(PDF) 43 Page - STMicroelectronics

部品番号 PSD835G2-70UI
部品情報  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2-70UI データシート(HTML) 43 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
42
MASTER
MCU
MCU - RD
MCU - RD
MCU - WR
SLAVE – WR
SLAVE – CS
MCU - WR
D [ 7:0]
D [ 7:0]
CPLD
DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MICRO ⇔ CELL
PORT A
SLAVE – READ
SLAVE
MCU
RD
WR
PSD835G2
Figure 15. Handshaking Communication Using Input Micro⇔Cells
The
PSD835G2
Functional
Blocks
(cont.)
9.2.2.7 External Chip Select
The CPLD also provides eight chip select outputs that can be used to select external
devices. The chip selects can be routed to either Port C or Port F, depending on the pin
declaration in the PSDsoft. Each chip select (ECS0-7) consists of one product term that can
be configured active high or low.
The output enable of the pin is controlled by either the output enable product term or the
Direction Register. (See Figure 16).
CPLD
AND
ARRAY
ECS PT
PORT C OR PORT F
ECS
TO PORT C OR F
ENABLE (.OE) PT
POLARITY
BIT
DIRECTION
REGISTER
PORT PIN
Figure 16. External Chip Select



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