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M32C/8B データシート(PDF) 223 Page - Renesas Technology Corp

部品番号 M32C/8B
部品情報  RENESAS MCU M16C FAMILY / M32C/80 SERIES
PDF  406 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/8B データシート(HTML) 223 Page - Renesas Technology Corp

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Under development
M32C/8B Group
17. Serial Interfaces
Preliminary specification
Specifications in this manual are tentative and subject to change.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008
Page 206 of 385
Figure 17.10
U0TB to U4TB Registers, U0RB to U4RB Registers
Symbol
Address
After Reset
RW
WO
UARTi Transmit Buffer Register (1) (i = 0 to 4)
U0TB to U2TB
U3TB, U4TB
036Bh - 036Ah, 02EBh - 02EAh, 033Bh - 033Ah
032Bh - 032Ah, 02FBh - 02FAh
Undefined
Undefined
Function
Bit Symbol
Transmit data (D7 to D0)
b7
b8
b15
b0
(b7-b0)
WO
Transmit data (D8)
(b8)
Unimplemented.
Write 0. Read as undefined value.
(b15-b9)
Symbol
Address
After Reset
RW
RO
UARTi Receive Buffer Register (i = 0 to 4)
U0RB to U2RB
U3RB, U4RB
036Fh - 036Eh, 02EFh - 02EEh, 033Fh - 033Eh
032Fh - 032Eh, 02FFh - 02FEh
Undefined
Undefined
Function
Bit Symbol
Received data (D7 to D0)
b7
b8
b15
b0
(b7-b0)
RO
Received data (D8)
(b8)
(b10-b9)
NOTE:
1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.
Bit Name
Unimplemented.
Write 0. Read as undefined value.
RW
0: Not detected (won)
1: Detected (lost)
Arbitration lost detect flag(1)
ABT
RO
0: No overrun error
1: Overrun error
Overrun error flag(2)
OER
RO
0: No framing error
1: Framing error
Framing error flag(2, 3)
FER
RO
0: No parity error
1: Parity error
Parity error flag(2, 3)
PER
RO
0 No error occurred
1: Error occurred
Error sum flag(2, 3)
SUM
NOTES:
1. Only a 0 can be written to the ABT bit.
2. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to
0 (receive operation disabled), bits OER, FER, PER and SUM become 0.
When all of bits OER, FER and PER become 0, the SUM bit also becomes 0.
Bits FER and PER become 0 by reading the low-order byte in the UiRB register.
3. Bits FER, PER and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode)
or 010b (I2C mode). A read from these bits returns undefined value.



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