M32CSLASH8B datasheet(227/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 210 of 385

Figure 17.12

Transmit and Receive Operations when Internal Clock is Selected

Transfer data from UARTi

receive shift register to UiRB

Communication stops because

TE bit = 0

Communication stops

because CTSi = “H”

TE bit in the

UiC1 register

i = 0 to 4

The above applies under the following conditions:

- UiMR register: CKDIR bit = 0 (internal clock)

- UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used)

CKPOL bit = 0 (transmit data output at the falling edge of the serial clock)

- UiC1 register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register)

NOTE:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

Internal clock

TI bit in the UiC1

Write data to the UiTB register

CTSi Input

CLKi output

TCLK

TXDi output

TXEP bit in the

UiC0 register

IR bit in the

SiTIC register

2(m + 1)

TC = TCLK =

fj = f1, f8, f2n(1)

m = Setting value of the UiBRG register

(00h to FFh)

D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5

Transfer data from UiTB register

to UARTi transmit shift register

RXDi input

D0 D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5

Set to 0 by an interrupt request acknowledgement or by a program

RI bit in the

UiC1 register

IR bit in the SiRIC

A read from the UiRB register

Set to 0 by an interrupt request acknowlegement or by a program

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

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