M32CSLASH8B datasheet(225/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 208 of 385

Table 17.2

Pin Settings in Clock Synchronous Mode

NOTES:

1. Set registers PS0, PS1, and PS3 after setting the other registers.

2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do

not generate an interrupt or a DMA or DMACII transfer between these two instructions.

3. P7_0 is an N-channel open drain output port.

4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the

Function Select Registers, the TXDi pin outputs an “H” signal until a transmit operation starts (the TXDi pin is in

a high-impedance state when N-channel open drain output is selected).

Port

Function

Bit Setting

PD6, PD7, PD9

Registers(2)

PSC Register

PSL0, PSL1, PSL3

Registers

PS0, PS1, PS3

Registers(1)(2)

P6_0

CTS0 input

PD6_0 = 0

−−

PS0_0 = 0

RTS0 output

−−

PSL0_0 = 0

PS0_0 = 1

P6_1

CLK0 input

PD6_1 = 0

−−

PS0_1 = 0

CLK0 output

−−

PSL0_1 = 0

PS0_1 = 1

P6_2

RXD0 input

PD6_2 = 0

−−

PS0_2 = 0

P6_3

TXD0 output(4)

−−

PSL0_3 = 0

PS0_3 = 1

P6_4

CTS1 input

PD6_4 = 0

−−

PS0_4 = 0

RTS1 output

−−

PSL0_4 = 0

PS0_4 = 1

P6_5

CLK1 input

PD6_5 = 0

−−

PS0_5 = 0

CLK1 output

−−

PSL0_5 = 0

PS0_5 = 1

P6_6

RXD1 input

PD6_6 = 0

−−

PS0_6 = 0

P6_7

TXD1 output(4)

−−

PSL0_7 = 0

PS0_7 = 1

P7_0(3)

TXD2 output(4)

−

PSC_0 = 0

PSL1_0 = 0

PS1_0 = 1

P7_1

RXD2 input

PD7_1 = 0

−−

PS1_1 = 0

P7_2

CLK2 input

PD7_2 = 0

−−

PS1_2 = 0

CLK2 output

−

PSC_2 = 0

PSL1_2 = 0

PS1_2 = 1

P7_3

CTS2 input

PD7_3 = 0

−−

PS1_3 = 0

RTS2 output

−

PSC_3 = 0

PSL1_3 = 0

PS1_3 = 1

P9_0

CLK3 input

PD9_0 = 0

−−

PS3_0 = 0

CLK3 output

−−

PSL3_0 = 0

PS3_0 = 1

P9_1

RXD3 input

PD9_1 = 0

−−

PS3_1 = 0

P9_2

TXD3 output(4)

−−

PSL3_2 = 0

PS3_2 = 1

P9_3

CTS3 input

PD9_3 = 0

−

PSL3_3 = 0

PS3_3 = 0

RTS3 output

−−

−

PS3_3 = 1

P9_4

CTS4 input

PD9_4 = 0

−

PSL3_4 = 0

PS3_4 = 0

RTS4 output

−−

−

PS3_4 = 1

P9_5

CLK4 input

PD9_5 = 0

−

PSL3_5 = 0

PS3_5 = 0

CLK4 output

−−

−

PS3_5 = 1

P9_6

TXD4 output(4)

−−

−

PS3_6 = 1

P9_7

RXD4 input

PD9_7 = 0

−−

PS3_7 = 0

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