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H838532H データシート(PDF) 67 Page - Renesas Technology Corp |
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H838532H データシート(HTML) 67 Page - Renesas Technology Corp |
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67 / 508 page  Section 2 CPU Rev. 1.00 May 30, 2008 Page 47 of 484 REJ09B0436-0100 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock ( φ) or a subclock (φ SUB). The period from a rising edge of φ or φ SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle. T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Read data Address Write data Internal data bus (write access) SUB φor φ Figure 2.9 On-Chip Memory Access Cycle |
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