H838532H datasheet(23/508 Pages) RENESAS

23 / 508 page

Section 1 Overview

Rev. 1.00 May 30, 2008 Page 3 of 484

REJ09B0436-0100

Classification

Module/

Function

Description

Clock

Clock pulse

generator

(CPG)

• Two clock generation circuits available

• Separate clock signals are provided for each of functional

modules

• Includes frequency division circuit, so the operating frequency is

selectable

• Seven low-power-consumption modes: Active (medium speed)

mode, sleep (high speed or medium speed) mode, subactive

mode, subsleep mode, standby mode, and watch mode

A/D converter

A/D

converter

(ADC)

• 10-bit resolution × eight input channels

• Sample and hold function included

• Conversion time:

12.4

µs per channel (with φ at 5-MHz operation)

• A/D conversion can be started by external trigger input

14-bit PWM

• 14 bits × one channel

• Four conversion periods selectable

• Pulse division method for less ripple

Timer A

• 8-bit timer

• Interval timer functionality: Eight internal clock sources are

selectable

• Clock time base functionality: Four overflow periods are

selectable

• Generates an interrupt upon overflow

• Timer output clock signals are selectable

Timer C

• 8-bit timer

• Eight clocks are selectable

• Auto-reload function supported

• Generates an interrupt upon overflow

• Up/down-counter switching is possible

Timer

Timer F

• 16-bit timer (also can be used as two independent 8-bit timers)

• Five clocks are selectable

• Output compare function supported

• Toggle output function supported

• Two interrupt sources: Compare match and overflow

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