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データシートサーチシステム |
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データシートサーチシステム |
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H838532H データシート(PDF) 86 Page - Renesas Technology Corp |
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H838532H データシート(HTML) 86 Page - Renesas Technology Corp |
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86 / 508 page  Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 66 of 484 REJ09B0436-0100 Bits 4 to 0: IRQ 4 to IRQ0 interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ 4 to IRQ0 interrupt requests. Bit n IENn Description 0 Disables interrupt requests from pin IRQn (initial value) 1 Enables interrupt requests from pin IRQn (n = 4 to 0) (3) Interrupt Enable Register 2 (IENR2) Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 — 0 R/W 4 IENTG 0 R/W 3 IENTFH 0 R/W 0 IENEC 0 R/W 2 IENTFL 0 R/W 1 IENTC 0 R/W IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT Description 0 Disables direct transfer interrupt requests (initial value) 1 Enables direct transfer interrupt requests Bit 6: A/D converter interrupt enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD Description 0 Disables A/D converter interrupt requests (initial value) 1 Enables A/D converter interrupt requests |
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