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H8S2245 データシート(PDF) 423 Page - Renesas Technology Corp |
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H8S2245 データシート(HTML) 423 Page - Renesas Technology Corp |
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423 / 818 page  Section 10 8-Bit Timers Rev.3.00 Mar. 26, 2007 Page 381 of 772 REJ09B0355-0300 10.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 10.6.1 Setting Module Stop Mode The TMR is enabled or disabled by setting the module stop control register. In the initial state, the TMR is disabled. After the module stop mode is canceled, registers can be accessed. For details, see section 18, Power-Down Modes. 10.6.2 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 10.10 shows this operation. φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 T1 T2 TCNT write cycle by CPU Figure 10.10 Contention between TCNT Write and Clear |
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