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H8S2245 データシート(PDF) 159 Page - Renesas Technology Corp |
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H8S2245 データシート(HTML) 159 Page - Renesas Technology Corp |
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159 / 818 page  Section 5 Interrupt Controller Rev.3.00 Mar. 26, 2007 Page 117 of 772 REJ09B0355-0300 Figure 5.4 shows a block diagram of the priority decision circuit. ICR UI I Default priority determination Vector number Interrupt acceptance control and 3-level mask control Interrupt source Interrupt control modes 0 and 1 Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control and 3-Level Control Interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bits Interrupt Control Mode I UI Selected Interrupts 00 * All interrupts (control level 1 has priority) 1 * NMI interrupts 10 * All interrupts (control level 1 has priority) 1 0 NMI and control level 1 interrupts 1 NMI interrupts Legend: *: Don't care |
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