データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

HD64F2149YV データシート(PDF) 388 Page - Renesas Technology Corp

部品番号 HD64F2149YV
部品情報  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV データシート(HTML) 388 Page - Renesas Technology Corp

Back Button HD64F2149YV Datasheet HTML 384Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 385Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 386Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 387Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 388Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 389Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 390Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 391Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 392Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 388 / 1075 page
background image
Section 12 8-Bit Timers
Rev. 3.00 Jan 18, 2006 page 360 of 1044
REJ09B0280-0300
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare-match of TCOR and TCNT.
OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the
effect of compare-match A on the output level, and both of them can be controlled independently.
Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If compare-
matches occur simultaneously, the output changes according to the compare-match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare-match occurs.
Bit 3
Bit 2
OS3
OS2
Description
0
0
No change when compare-match B occurs
(Initial value)
1
0 is output when compare-match B occurs
1
0
1 is output when compare-match B occurs
1
Output is inverted when compare-match B occurs (toggle output)
Bit 1
Bit 0
OS1
OS0
Description
0
0
No change when compare-match A occurs
(Initial value)
1
0 is output when compare-match A occurs
1
0
1 is output when compare-match A occurs
1
Output is inverted when compare-match A occurs (toggle output)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com