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HD64F2149YV データシート(PDF) 92 Page - Renesas Technology Corp |
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HD64F2149YV データシート(HTML) 92 Page - Renesas Technology Corp |
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92 / 1075 page  Section 2 CPU Rev. 3.00 Jan 18, 2006 page 64 of 1044 REJ09B0280-0300 (a) Normal Mode (b) Advanced Mode Branch address Specified by @aa:8 Specified by @aa:8 Reserved Branch address Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. |
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