HD64F2149YV datasheet(96/1075 Pages) RENESAS

部品番号	HD64F2149YV

部品情報	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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メーカー	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 68 of 1044

REJ09B0280-0300

2.8

Processing States

2.8.1

Overview

The CPU has five main processing states: the reset state, exception-handling state, program

execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the

processing states. Figure 2.15 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been

initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal

processing flow in response to a reset, interrupt, or trap

instruction.

Program execution

state

The CPU executes program instructions in sequence.

Bus-released state

The external bus has been released in response to a bus

request signal from a bus master other than the CPU.

Power-down state

CPU operation is stopped

to conserve power.*

Sleep mode

Software standby

mode

Hardware standby

mode

Processing

states

Note: * The power-down state also includes a medium-speed mode, module stop mode,

sub-active mode, sub-sleep mode, and watch mode.

Figure 2.14 Processing States

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